1. Field of the Invention
The present invention generally relates to a synchronous semiconductor memory device, and more specifically, to a technology of reducing an operation current by limiting unnecessary internal operations with a command interval defined in a standard.
2. Description of the Prior Art
FIG. 1 is a block diagram illustrating a conventional synchronous semiconductor memory device. Here, the conventional synchronous semiconductor memory device that receives a plurality of commands and addresses is operated synchronously with respect to a clock.
The synchronous semiconductor memory device comprises a plurality of pads 1˜7, a plurality of buffers 11˜17, a clock driving unit 21, a state machine 22 and an address latch 23.
The plurality of pads 1˜7 includes a clock pad 1 for receiving clocks CK and /CK, command pads 2˜5, and address pads 6 and 7 for receiving a plurality of addresses A0˜Ai. Here, the commands pads 2˜5 include a chip selection command pad 2 for receiving a chip selection command /CS, a /RAS command pad 3 for receiving a row address strobe command /RAS, a /CAS command pad 4 for receiving a column address strobe command /CAS, and a /WE command pad 5 for receiving a write enable command /WE.
The plurality of buffers 11˜17 includes a clock buffer 11 for buffering the clocks CK and /CK applied to the clock pad 1, a plurality of command buffers 13˜15 for buffering a plurality of commands such as /CS, /RAS, /CAS and /WE applied to the command pads 2˜5, and address buffers 16 and 17 for buffering the plurality of addresses A0˜Ai applied to the address pads 6 and 7.
The clock driving unit 21 drives a clock CLK0 outputted from the clock buffer 11 to generate an internal clock iCLK.
The command decoder 22 generates internal commands such as MRS (Mode Register Set), ACT (active), WR (write) and RD (read) in response to commands outputted from the plurality of command buffers 12˜15 synchronously with respect to the internal clock iCLK.
The address latch 23 generates latch addresses LA0˜LAi in response to addresses outputted from the address buffers 16 and 17 synchronously with respect to the internal clock iCLK.
FIG. 2 is a timing diagram illustrating the operation of the synchronous semiconductor memory device of FIG. 1.
The address latch 23 latches the address synchronously with respect to the internal clock iCLK like the operation of the command decoder 22. As a result, the address latch 23 latches new addresses at every clock regardless of operation commands.
Since the JEDEC standard of tMRD (Mode register set command cycle time) and tCCD (CAS to CAS delay command cycle time) defines 2 clocks, the address of the clock after commands such as MRS, RD and WR is not effectively used in the synchronous semiconductor memory device.
However, since the conventional synchronous semiconductor memory device latches the addresses synchronously with respect to the internal clock iCLK regardless of input commands, unnecessary operation current is consumed.